This invention relates to semiconductor integrated circuits, methods of designing semiconductor integrated circuits, and cell libraries used to design semiconductor integrated circuits. More specifically, this invention relates to semiconductor integrated circuits and methods of designing semiconductor integrated circuits and cell libraries that enable precise adjustment of delay times.
In semiconductor integrated circuits, various logic circuits that conduct various logical operations on various variables are formed to realize desired functions. These logic circuits have signal routes that diverge and merge complexly, and timings of signals at various portions in the signal route that must be synchronized. Accordingly, delay circuits are provided at necessary portions on the signal route in order to adjust the timings.
Generally, buffers are used as delay circuits for adjusting the timings. That is, a plurality of buffers is connected in series at necessary portions in the signal route, and the number of serially connected buffers is selected in order to provide a desired delay time. In such an instance, the delay time can only be adjusted with a step of the delay time of one buffer.
Circuits that can adjust the delay time with a shorter step compared with the case of the serially connected buffers are proposed. For example, Japanese Laid-open Patent Hei 9-191239 discloses a delay circuit in which the delay time can be adjusted with a control signal input to a control terminal. Similar delay circuits are also disclosed in Japanese Laid-open Patent Hei 7-202653 and Japanese Laid-open Patent 2004-135333.
On the other hand, standard cells are generally utilized in designing semiconductor integrated circuits that perform various logical operations. That is, layouts of transistors and interconnections between the transistors necessary to realize various logical functions are prepared beforehand and registered in a library as standard cells. For example, basic gates such as inverters, buffers, AND gates, OR gates, NAND gates, and NOR gates, and other cells having functions of various combinations of the basic gates are registered in the cell library as standard cells. Standard cells that are required to fulfill the specification of each semiconductor integrated circuit are selected from the cell library, and connected with each other. As a result, signal routes are formed, and logic circuits that constitutes a semiconductor integrated circuit or a circuit block including a plurality of logic circuits are constructed.
In order to utilize the delay circuits described in the above-cited reference in the design of semiconductor integrated circuits using the standard cell technique, standard cells of the delay circuits should be prepared and registered in the cell library. However, such procedures are lengthy, cumbersome, and not easily implemented.